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<\/a><\/p>\n(To get more details about NFV architecture<\/a>, I recommend reading my blog on cheat sheet on NFV architecture<\/a> or NFV MANO)<\/a><\/p>\n As shown clearly in the NFV Infrastructure block above, the Compute Domain includes both the compute hardware and the storage hardware. So Compute Domain is the superset, of which the Compute HW\/node is just one part.<\/p>\n Surprised, aren\u2019t you? How many of you were thinking of storage as a part of the compute domain?<\/p>\n So let\u2019s go deeper into what is included in the compute domain:<\/p>\n Thee three Parts of Compute Domain<\/p>\n In COTS (Common of the shelf) architecture, the compute node includes the multi core processor and chipset which may include the following physical resources<\/p>\n \u00b7 CPU and chipset (for example x86, ARM etc.)<\/p>\n \u00b7 Memory subset.<\/p>\n \u00b7 Optional hardware accelerators ( e.g. co-processor)<\/p>\n \u00b7 NICs ( Network Interface cards with optional accelerators)<\/p>\n \u00b7 Storage internal to blade (nonvolatile memory, local disk storage)<\/p>\n \u00b7 BIOS\/Boot loader ( part of execution environment)<\/p>\n A COTS server blade is an example of compute node<\/p>\n As you can see that I mentioned NIC as part of the compute node in earlier section. Which is true. Because, in the case above the NIC capability is on board the server. However there is a recent trend of a disaggregated model (For example Open Compute Project\u00a0 OCP<\/a>). In this form-factor, the CPU blades\/chassis are separated from the NIC\/Accelerator chassis, and Storage chassis. Inter-connection between the blades\/chassis could be over optical fiber. So because of this reason NIC is mentioned separately as it owes its own explanation owing to its importance.<\/p>\n The main function of NIC is to provide network I\/O functionality to\/from CPU.<\/p>\n The vision of NFV is to run network functions on standard generic x86 servers. In practice however there are many I\/O intensive applications ( for example virtual router) that would demand acceleration technologies to help improve I\/O throughput of the machines.<\/p>\n Some hardware acceleration techniques involve the following:<\/p>\n \u00b7 Hardware acceleration such as Digital Signal Processing (DSP), packet header processing, packet buffering and scheduling.<\/p>\n \u00b7 Cache Management features.<\/p>\n Additions to the Instruction Set Architecture (ISA) (e.g. x86, ARMv8, etc.) which implement new software acceleration features.<\/p>\n The storage infrastructure includes different primary classifications of drives: Hard Disk Drives (HDDs), Solid State Disks (SDDs), Cache storage etc. which needs to be understood.<\/p>\n A hard disk drive<\/b> (HDD<\/b>), hard disk<\/b>, is a data storage device that uses magnetic storage to store and retrieve digital information using one or more rigid rapidly rotating disks (platters) coated with magnetic material. The platters are paired with magnetic heads which read and write data on platter surface. Data is accessed in a random-access manner, which has the advantage that data can be retrieved in any order and not only sequentially. HDDs is non-volatile storage. Which means, it can retaining stored data even when powered off.<\/p>\n1. Compute Node<\/h3>\n
2. Network Interface Card\u00a0 (NIC) and I\/O Accelerators<\/h3>\n
3. Storage Building Block<\/h3>\n
3.1 Hard Disk Drives<\/h4>\n
3.2 Solid State Disks (SSD)<\/h4>\n